FIG. 1A shows a circuit diagram of a conventional level shifter circuit 10. The circuit 10 includes a first input transistor 12 and a second input transistor 14. The transistors 12 and 14 are n-channel MOSFET devices. The gate of the first input transistor 12 is configured to receive an input signal IN and the gate of the second input transistor 14 is configured to receive a complement input signal INN. The complementary input signals IN and INN are referenced to a first power supply domain with a positive voltage Vdd and a ground voltage Gnd. In this configuration, the complementary input signals IN and INN may be digital logic signals having a logic “1” voltage at the positive voltage Vdd and a logic “0” voltage at the ground voltage Gnd. The complement input signal INN may be generated from the input signal IN by a CMOS inverter circuit 18 that is powered at supply nodes from the Vdd and Gnd voltages. The body terminal of input transistor 12 is configured to receive the input signal IN and the body terminal of input transistor 14 is configured to receive the complement input signal INN.
The level shifter circuit 10 is powered from a second power supply domain with a positive voltage Vdde and a ground voltage Gnde. Source terminals of the transistors 12 and 14 are connected to a power supply node at the ground voltage Gnde. The drain terminal of the first input transistor 12 is connected to a complement output node OUTN and the drain terminal of the second input transistor 14 is connected to an output node OUT.
The level shifter circuit 10 further includes a pair of cross-coupled load transistors coupled through the output nodes OUT and OUTN to the first and second input transistors 12 and 14. More specifically, a first load transistor 22 has a drain terminal connected to the complement output node OUTN (and the drain of transistor 12) and a second load transistor 24 has a drain terminal connected to the output node OUT (and the drain of transistor 14). Source terminals of the transistors 22 and 24 are connected to a power supply node at the positive voltage Vdde. The gate of load transistor 22 is connected to the drain of load transistor 24 at the output node OUT, and gate of load transistor 24 is connected to the drain of load transistor 22 at the output node OUTN.
The level shifter circuit 10 operates to voltage shift the complementary input signals IN and INN from the first power supply domain to generate the complementary output signals at the output nodes OUT and OUTN in the second power supply domain. It is recognized, however, by those skilled in the art that the level shifter circuit 10 is not functional at very low supply voltage levels. At very low voltages of the first power supply domain, for example, below Vdd=0.45 V, the circuit is not able to level shift from low voltage to high voltage levels.
There is accordingly a need in the art for a level shifting circuit offering functionality when voltage shifting signals between power supply domains where the relatively lower level power supply domain uses a low voltage positive power supply voltage.
FIG. 1B shows a circuit diagram of a level shifter 50. See, for example, Lutkemeier, et al., “A Subthreshold to Above-Threshold Level Shifter Comprising a Wilson Current Mirror,” IEEE Trans. on Circuits and Systems-II: Express Briefs, vol. 57. no. 9, 2010, FIG. 3 (incorporated by reference). The circuit 50 includes a first input transistor 52 and a second input transistor 54. The transistors 52 and 54 are n-channel MOSFET devices. The gate of the first input transistor 52 is configured to receive an input signal IN and the gate of the second input transistor 54 is configured to receive a complement input signal INN. The complementary input signals IN and INN are referenced to a first power supply domain with a positive voltage Vdd and a ground voltage Gnd. In this configuration, the complementary input signals IN and INN may be digital logic signals having a logic “1” voltage at the positive voltage Vdd and a logic “0” voltage at the ground voltage Gnd. The complement input signal INN may be generated from the input signal IN by a CMOS inverter circuit 58 that is powered at supply nodes from the Vdd and Gnd voltages.
The level shifter circuit 50 is powered from a second power supply domain with a positive voltage Vdde and a ground voltage Gnde. Source terminals of the transistors 52 and 54 are connected to a power supply node at the ground voltage Gnde. The drain terminal of the first input transistor 52 is connected to node 66 and the drain terminal of the second input transistor 54 is connected to node 68 which forms the output node OUT.
While the level shifter 10 of FIG. 1A used a latch circuit as the load for the input transistors, the level shifter 50 of FIG. 1B instead uses a Wilson current mirror 70 as the load. The current mirror 70 comprises a diode-connected p-channel MOSFET device 72 having a gate terminal connected to the gate terminal of a p-channel MOSFET device 74. Source terminals of the transistors 72 and 74 are connected to the positive voltage Vdde. The drain terminal of transistor 72 is coupled to the node 66 through the source-drain path of p-channel MOSFET device 74. The drain terminal of transistor 74 is coupled to the node 68. The Wilson current mirror 70 is operated in the overdrive region to ensure that no current flows through transistor 52 or 54 if that transistor is turned off.
The functionality of this circuit 50 similarly suffers when voltage shifting signals between power supply domains where the relatively lower level power supply domain uses a low voltage positive power supply voltage.